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| MC68HC705J2/D Rev. 1 HC05 MC68HC7 0 5 J 2 TECHNICAL DATA TABLE OF CONTENTS Section Title Page 1.1 1.2 SECTION 1 INTRODUCTION Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 SECTION 2 PIN DESCRIPTIONS 2.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 External Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 IRQ/Vpp (External Interrupt Request/Programming Voltage . . . . . . . . . . . . . . 2.4 2-2 2-2 2-2 2-2 2-3 2-4 2-4 SECTION 3 PARALLEL I/O 3.1 I/O Port Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.1.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 SECTION 4 CENTRAL PROCESSOR UNIT 4.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5.1 Half-Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5.2 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5.3 Negative Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5.4 Zero Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5.5 Carry/Borrow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC705J2 Rev. 1 4-1 4-2 4-2 4-2 4-3 4-3 4-3 4-3 4-3 4-4 4-4 4-4 4-4 4-4 4-7 MOTOROLA iii TABLE OF CONTENTS Section Title Page SECTION 5 RESETS AND INTERRUPTS 5.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1.1 Timer Overflow Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1.2 Real-Time Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SECTION 6 MEMORY 6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Input/Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3.1 EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3.2 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.4 Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-1 5-2 5-2 5-2 5-3 5-4 5-4 5-4 5-6 5-6 6-1 6-1 6-1 6-4 6-4 6-5 6-5 6-6 7.1 7.2 7.3 SECTION 7 TIMER Timer Counter Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Timer Control and Status Register (TCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 COP Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 SECTION 8 BOOTLOADER MODE 8.1 Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 External EPROM Downloading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Host Downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-1 8-3 8-4 9.1 9.2 9.3 SECTION 9 MC68HC05J1 EMULATION MODE Bootloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 MC68HC05J1 Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 MC68HC705J2 Rev. 1 MOTOROLA iv TABLE OF CONTENTS Section Title Page 9SECTION 10 INSTRUCTION SET 10.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.7 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10-1 10-1 10-2 10-2 10-2 10-2 10-3 10-3 10-4 10-4 10-5 10-5 10-7 10-7 10-8 11.3 SECTION 11 ELECTRICAL SPECIFICATIONS Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 MC68HC705J2 Rev. 1 MOTOROLA v MOTOROLA vi MC68HC705J2 Rev. 1 LIST OF FIGURES Figure 1-2 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 4-1 4-2 4-3 5-1 5-2 5-3 5-4 6-1 6-2 6-3 7-1 7-2 7-3 7-4 8-1 8-2 9-1 Title Page MC68HC705J2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Crystal/Ceramic Resonator Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Parallel I/O Port Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-3 3-3 3-4 3-4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 STOP Instruction Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 WAIT Instruction Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Trigger Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5-3 5-5 5-6 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 1/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 EPROM Programming Register (PROG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Counter Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Control and Status Register (TCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-2 7-2 7-4 Bootloader Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 MC68HC05J1 Emulation Mode Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 11-1 Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11-2 Typical High-Side Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11-3 Typical Low-Side Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 MC68HC705L5 Rev. 1 MOTOROLA vii LIST OF FIGURES Figure 11-4 11-5 11-6 11-7 11-8 11-9 Title Page Typical Supply Current vs Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Maximum Supply Current vs Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . 11-6 External Interrupt Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 STOP Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 External Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 MOTOROLA viii MC68HC705L5 REV. 1.0 LIST OF TABLES Table 3-1 7-1 8-1 10-1 10-2 10-3 10-4 10-5 10-6 10-7 11-1 11-2 11-3 11-4 11-5 11-6 Title Page I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Real-Time Interrupt Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Bootloader Function Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Read-Modify-Write Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Jump and Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics (VDD = 3.3 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . Control Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Timing (VDD = 3.3 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11-1 11-3 11-4 11-7 11-8 MC68HC705L5 REV. 1.0 MOTOROLA ix MOTOROLA x MC68HC705L5 Rev. 1 SECTION 1 INTRODUCTION The MC68HC705J2 is a member of the low-cost, high-performance M68HC05 Family of 8-bit microcontroller units (MCUs). The high-density, complementary metal-oxide semiconductor (HCMOS) M68HC05 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the popular M68HC05 central processor unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types. The MC68HC705J2 is an expansion of the MC68HC05J1 design. On-chip memory is enhanced with 2 Kbytes of erasable, programmable ROM (EPROM), 112 Kbytes of RAM, and a bootloader ROM. 1.1 Features The MCU features include the following: * * * * * * * * * * * * * * * * * * Popular M68HC05 CPU Memory-Mapped Input/Output (I/O) Registers 2064 Bytes of User EPROM Including 16 User Vector Locations 112 Bytes of Static RAM (SRAM) 14 Bidirectional I/O Pins Fully Static Operation With No Minimum Clock Speed On-Chip Oscillator With Crystal/Ceramic Resonator Connections 15-Bit Multifunction Timer Real-Time Interrupt Circuit Bootloader ROM Power-Saving STOP, WAIT, and Data Retention Modes MC68HC05J1 Emulation Mode Selectable Edge-Sensitive or Edge- and Level-Sensitive External Interrupt Trigger Selectable Computer Operating Properly (COP) Timer 8 x 8 Unsigned Multiply Instruction One Time Programmable 20-Pin Dual-in-Line Package (DIP) One Time Programmable 20-Pin Small Outline Integrated Circuit (SOIC) Windowed 20-Pin Cerdip MC68HC705J2 INTRODUCTION MOTOROLA 1-1 1.2 Structure Figure 1-1 shows the organization of the MC68HC705J2 EPROM MCU. USER EPROM -- 2064 BY BOOTLOADER ROM -- 239 B SRAM -- 112 BYT DATA DIRECTION A PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 7 IRQ/V PP RESET RST 5 15 7 0000000011 15 11 00000 0 ACCUMULATO 7 0 INDEX REGISTER 0 STACK POINTE 0 PROGRAM COUNTE DATA DIRECTION B PORT A M68HC05 CPU 7 0 1 1 1 H I NZ C CONDITION CODE REGISTE OSC1 OSC2 OSCILLATOR DIVIDE BY 2 f op PB5 PB4 PB3 PB2 PB1 PB0 COP TIMER AND ILLEGAL ADDRESS DET VDD V SS 15-STAGE MULTIFUNCTION TIME POWER Figure 1-1. MC68HC705J2 Block Diagram MOTOROLA 1-2 INTRODUCTION MC68HC705J2 PORT B SECTION 2 PIN DESCRIPTIONS This section describes the function of each pin. assignments. Figure 2-1 shows the pin OSC1 1 2 20 RESET IRQ/V PP PA0 OSC2 19 18 PB5 PB4 3 4 17 16 PA1 PA2 OSC1 OSC2 PB5 PB4 PB3 PB2 PB1 PB0 VDD VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RESET IRQ/VP P PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB3 PB2 5 6 15 14 PA3 PA4 PB1 PB0 VDD VSS 7 8 13 12 PA5 PA6 9 10 11 PA7 DIP/CERDI SOIC Figure 2-1. Pin Assignments MC68HC705J2 PIN DESCRIPTIONS MOTOROLA 2-1 2.1 VD D and VS S VDD and VSS are the power supply and ground pins. The MCU operates from a single 5-V power supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, take special care to provide good power supply bypassing at the MCU. Use bypass capacitors with good high-frequency characteristics, and position them as close to the MCU as possible. Bypassing requirements vary, depending on how heavily loaded the MCU pins are. 2.2 OSC1 and OSC2 The OSC1 and OSC2 pins are the control connections for the on-chip oscillator. Connect any of the following to the OSC1 and OSC2 pins: * A crystal (Refer to Figure 2-2.) * A ceramic resonator (Refer to Figure 2-2.) * An external clock signal (Refer to Figure 2-3.) The MCU divides the frequency, fosc, of the oscillator or external clock source by two to produce the internal operating frequency, fop. 2.2.1 Crystal The circuit in Figure 2-2 shows a typical crystal oscillator circuit for a parallel resonant crystal. Follow the crystal supplier's recommendations, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances. Mount the crystal and components as close as possible to the pins for start-up stabilization and to minimize output distortion. 2.2.2 Ceramic Resonator In cost-sensitive applications, use a ceramic resonator in place of the crystal. Use the circuit in Figure 2-2 for a ceramic resonator, and follow the resonator manufacturer's recommendations, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances. MOTOROLA 2-2 PIN DESCRIPTIONS MC68HC705J2 STOP OSC1 4.7 M OSC2 XTAL 37 pF 37 pF Figure 2-2. Crystal/Ceramic Resonator Connections 2.2.3 External Clock An external clock from another CMOS-compatible device can drive the OSC1 input, with the OSC2 pin not connected, as Figure 2-3 shows. STOP OSC1 OSC2 NOT CONNECTE EXTERNAL CMOS CLOCK Figure 2-3. External Clock Connections MC68HC705J2 PIN DESCRIPTIONS MOTOROLA 2-3 2.3 R E S E T A zero on the RESET pin forces the MCU to a known start-up state. See 5 . 1 Resets for more information. 2.4 IRQ /VPP (External Interrupt Request/Programming Voltage) The IRQ /VPP pin has the following functions: * Applying asynchronous external interrupt signals (See 5.2 Interrupts.) * Applying the programming voltage for programming the EPROM (See 6.1.3.1 EPROM Programming and 8.1.1 External EPROM Downloading.) MOTOROLA 2-4 PIN DESCRIPTIONS MC68HC705J2 SECTION 3 PARALLEL I/O This section describes the two bidirectional I/O ports. 3.1 I/O Port Function The 14 I/O pins form two I/O ports. Each I/O pin is programmable as an input or an output. The contents of a port data direction register (DDR) determine the data direction for the port. Writing a 1 to a DDR bit enables the output buffer for the associated port pin; a 0 disables the output buffer. A reset initializes all implemented DDR bits to 0, configuring all I/O pins as inputs. NOTE Connect any unused inputs and I/O pins to an appropriate logical level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces the possibility of electrostatic damage. A reset does not initialize the two port data registers. The port data registers for ports A and B are at addresses $0000 and $0001. To avoid undefined levels, write the data registers before writing the data direction registers. With an I/O port pin programmed as an output, reading the pin actually reads the value of the output data latch and not the voltage on the pin itself. When a pin is programmed as an input, reading the port bit reads the voltage level on the I/O pin. The output data latch can always be written, regardless of the state of its DDR bit. Refer to Figure 3-1 for typical port circuitry, and to Table 3-1 for a summary of I/O pin functions. MC68HC705J2 PARALLEL I/O MOTOROLA 3-1 CONNECTIONS TO INTERNAL DATA BUS DATA DIRECTIO REGISTER BIT LATCHED OUTPUT DATA BIT [3] I/O PIN [1] [2] [1] Output buffer enables latched output to drive I/O pin when DDR bit is 1 (output mode). [2] Input buffer enabled when DDR bit is 0 (input mode). [3] Input buffer enabled when DDR bit is 1 (output mode). Figure 3-1. Parallel I/O Port Circuit Table 3-1. I/O Pin Functions R/W 0 0 1 1 DDR Bit 0 1 0 1 I/O Pin Function The I/O pin is an input. Data is written into the output data latch. Data is written into the output data latch, which drives the I/O pin. The state of the I/O pin is read. The I/O pin is an output. The output data latch is read. NOTE: R/W is an internal MCU signal. MOTOROLA 3-2 PARALLEL I/O MC68HC705J2 3.2 Port A Port A is an 8-bit general-purpose bidirectional I/O port. The contents of DDRA determine whether each pin is an input or an output. Figures 3-2 and 3-3 show the port A data register and DDRA. PORTA -- Port A Data Register Bit 7 PA7 RESET: 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 Bit 0 PA0 $0000 NOT CHANGED BY RESET Figure 3-2. Port A Data Register PA7-PA0 -- Port A Data Bits These read/write bits are software-programmable. Data direction of each bit is under the control of the corresponding DDRA bit. DDRA -- Port A Data Direction Register Bit 7 0 RESET: 0 6 0 0 5 DDRA5 0 4 DDRA4 0 3 DDRA3 0 2 DDRA2 0 1 DDRA1 0 Bit 0 DDRA0 0 $0004 Figure 3-3. Port A Data Direction Register DDRA7-DDRA0 -- Port A Data Direction Bits These read/write bits control port A data direction. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input MC68HC705J2 PARALLEL I/O MOTOROLA 3-3 3.3 Port B Port B is a 6-bit general-purpose bidirectional I/O port. The contents of DDRB determine whether each pin is an input or an output. Figures 3-4 and 3-5 show the port B data register and DDRB. PORTB -- Port B Data Register Bit 7 0 RESET: 6 0 5 PB5 4 PB4 3 PB3 2 PB2 1 PB1 Bit 0 PB0 $0001 NOT CHANGED BY RESET Figure 3-4. Port B Data Register PB5-PB0 -- Port B Data Bits These read/write bits are software-programmable. Data direction of each bit is under the control of the corresponding DDRA bit. DDRB -- Port B Data Direction Register Bit 7 DDRB7 RESET: 0 6 DDRB6 0 5 DDRB5 0 4 DDRB4 0 3 DDRB3 0 2 DDRB2 0 1 DDRB1 0 Bit 0 DDRB0 0 $0005 Figure 3-5. Port B Data Direction Register DDRB7-DDRB0 -- Port B Data Direction Bits These read/write bits control port B data direction. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input MOTOROLA 3-4 PARALLEL I/O MC68HC705J2 SECTION 4 CENTRAL PROCESSOR UNIT This section describes the registers, instruction set, and addressing modes of the M68HC05 central processor unit (CPU). 4.1 CPU Registers Figure 4-1 shows the five CPU registers. These are hard-wired registers within the CPU and are not part of the memory map. 7 A 7 X 15 0 15 0 0 0 0 0 0 0 0 0 0 8 PCH 7 1 1 5 1 1 7 PCL 4 H I N Z 6 1 5 SP 0 ACCUMULATOR (A) 0 INDEX REGISTER (X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 0 C CONDITION CODE REGISTER (CCR) 12 11* 0 CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG *Bit 11 of the program counter is fixed at 0 in MC68HC05J1 emulation mode. Figure 4-1. Programming Model MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-1 4.1.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and results of arithmetic and nonarithmetic operations. 4.1.2 Index Register The 8-bit index register can perform two functions: * Indexed addressing * Temporary storage In indexed addressing, the CPU uses the byte in the index register to determine the conditional address of the operand. See 4.3.5 Indexed, No Offset, 4.3.6 Indexed, 8-Bit Offset, and 4.3.7 Indexed, 16-Bit Offset. The index register can also serve as an auxiliary accumulator for temporary storage. 4.1.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next free location on the stack. During a reset or after the reset stack pointer (RSP) instruction, the stack pointer contents are preset to $00FF. The address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. The ten most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00C0 and begins writing over the previously stored data. A subroutine uses two stack locations; an interrupt uses five locations. MOTOROLA 4-2 CENTRAL PROCESSOR UNIT MC68HC705J2 4.1.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. The four most significant bits of the program counter are permanently fixed at 0000. In MC68HC05J1 emulation mode, the five most significant bits are fixed at 00000. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 4.1.5 Condition Code Register The condition code register is an 8-bit register whose three most significant bits are permanently fixed at 111. The condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. The following paragraphs describe the functions of the condition code register. 4.1.5.1 Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD or ADC operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. 4.1.5.2 Interrupt Mask Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is zero, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the CPU processes the latched interrupt as soon as the interrupt mask is cleared again. A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its cleared state. After any reset, the interrupt mask is set and can be cleared only by a software instruction. MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-3 4.1.5.3 Negative Flag The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. Bit 7 of the negative result is automatically set, so the negative flag can be used to check an often-tested bit by assigning it to bit 7 of a register or memory location. Loading the accumulator with the contents of that register or location then sets or clears the negative flag according to the state of the tested bit. 4.1.5.4 Zero Flag The CPU sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a $00. 4.1.5.5 Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag. 4.2 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logical operations defined by the instruction set. The binary arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal processor cycles to complete this chain of operations. 4.3 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data. These addressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight addressing modes are as follows: * * * * * * * * Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative MOTOROLA 4-4 CENTRAL PROCESSOR UNIT MC68HC705J2 4.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Other inherent instructions are those that act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no memory address and are one byte long. Table 4-1 lists the instructions that use the inherent addressing mode. Table 4-1. Inherent Addressing Instructions Instruction Arithmetic Shift Left Arithmetic Shift Right Clear Carry Bit Clear Interrupt Mask Clear Complement Decrement Increment Logical Shift Left Logical Shift Right Multiply Negate No Operation Rotate Left through Carry Rotate Right through Carry Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Enable IRQ and Stop Oscillator Software Interrupt Transfer Accumulator to Index Register Test for Negative or Zero Transfer Index Register to Accumulator Enable Interrupt and Half Processor Mnemonic ASLA, ASLX ASRA, ASRX CLC CLI CLRA, CLRX COMA, COMX DECA, DECX INCA, INCX LSLA, LSLX LSRA, LSRX MUL NEGA, NEGX NOP ROLA, ROLX RORA, RORX RSP RTI RTS SEC SEI STOP SWI TAX TSTA, TSTX TXA WAIT MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-5 4.3.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no memory address and are two bytes long. The opcode is the first byte and the immediate data value is the second byte. Table 4-2 lists the instructions that use the immediate addressing mode. Table 4-2. Immediate Addressing Instructions Instruction Add with Carry Add Logical AND Bit Test Memory with Accumulator Compare Accumulator with Memory Compare Index Register with Memory Exclusive OR Memory with Accumulator Load Accumulator from Memory Load Index Register from Memory Inclusive OR Subtract with Carry Subtract Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX ORA SBC SUB 4.3.3 Direct Direct instructions can access any of the first 256 memory addresses with only two bytes. The first byte is the opcode and the second byte is the low byte of the operand's address. In the direct addressing mode, the CPU automatically uses $00 as the high byte of the operand's address. BRSET and BRCLR are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. Table 4-3 lists the instructions that use the direct addressing mode. MOTOROLA 4-6 CENTRAL PROCESSOR UNIT MC68HC705J2 Table 4-3. Direct Addressing Instructions Instruction Add with Carry Add Logical AND Arithmetic Shift Left Arithmetic Shift Right Clear Bit in Memory Bit Test Memory with Accumulator Branch if Bit n Is Clear Branch if Bit n Is Set Set Bit in Memory Clear Compare Accumulator with Memory Complement Compare Index Register with Memory Decrement Exclusive OR Memory with Accumulator Increment Jump Jump to Subroutine Load Accumulator from Memory Load Index Register from Memory Logical Shift Left Logical Shift Right Negate Inclusive OR Rotate Left through Carry Rotate Right through Carry Subtract with Carry Store Accumulator in Memory Store Index Register in Memory Subtract Test for Negtative or Zero Mnemonic ADC ADD AND ASL ASR BCLR BIT BRCLR BRSET BSET CLR CMP COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR NEG ORA ROL ROR SBC STA STX SUB TST MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-7 4.3.4 Extended Extended instructions can access any address in memory with only three bytes. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand's address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. Table 4-4 lists the instructions that use the extended addressing mode. Table 4-4. Extended Addressing Instructions Instruction Add with Carry Add Logical AND Bit Test Memory with Accumulator Compare Accumulator with Memory Compare Index Register with Memory Exclusive OR Memory with Accumulator Jump Jump to Subroutine Load Accumulator from Memory Load Index Register from Memory Inclusive OR Subtract with Carry Store Accumulator in Memory Store Index Register in Memory Subtract Mnemonic ADC ADD AND BIT CMP CPX EOR JMP JSR LDA LDX ORA SBC STA STX SUB MOTOROLA 4-8 CENTRAL PROCESSOR UNIT MC68HC705J2 4.3.5 Indexed, No Offset Indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the operand's conditional address. The CPU automatically uses $00 as the high byte of the operand's conditional address, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location. Table 4-5 lists the instructions that use the indexed, no offset addressing mode. 4.3.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the conditional address of the operand. These instructions can address locations $0000-$01FE. Indexed, 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value would typically be in the index register, and the address of the beginning of the table would be in the byte following the opcode. Table 4-5 lists the instructions that use the indexed, 8-bit offset addressing mode. 4.3.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. These instructions can address any location in memory. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. Table 4-5 lists the instructions that can use the indexed, 16-bit offset addressing mode. MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-9 Table 4-5. Indexed Addressing Instructions Instruction Add with Carry Add Logical AND Arithmetic Shift Left Arithmetic Shift Right Bit Test Memory with Accumulator Clear Compare Accumulator with Memory Complement Compare Index Register with Memory Decrement Exclusive OR Memory with Accumulator Increment Jump Jump to Subroutine Load Accumulator from Memory Load Index Register from Memory Logical Shift Left Logical Shift Right Negate Inclusive OR Rotate Left through Carry Rotate Right through Carry Subtract with Carry Store Accumulator in Memory Store Index Register in Memory Subtract Test for Negative or Zero Mnemonic ADC ADD AND ASL ASR BIT CLR CMP COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR NEG ORA ROL ROR SBC STA STX SUB TST No Offset 8-Bit Offset 16-Bit Offset MOTOROLA 4-10 CENTRAL PROCESSOR UNIT MC68HC705J2 4.3.8 Relative The relative addressing mode is only for branch instructions and bit test and branch instructions. The CPU finds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter if the branch condition is true. If the branch condition is not true, the CPU goes to the next instruction. To permit branching either forward or backward, the offset is a signed, two's complement byte that gives a branching range of -127 to +128 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. Table 4-6 lists the instructions that use the relative addressing mode. Table 4-6. Relative Addressing Instructions Instruction Branch if Carry Clear Branch if Carry Set Branch if Equal Branch if Half-Carry Clear Branch if Half-Carry Set Branch if Higher Branch if Higher or Same Branch if Interrupt Line iHigh Branch if Interrupt Line Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit n Clear Branch if Bit n Set Branch Never Branch to Subroutine Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRSET BRN BSR MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-11 4.4 Instruction Set The MCU uses all the instructions available in the M146805 CMOS Family plus the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator and the index register. The CPU stores the high-order product in the index register, and the low-order product in the accumulator. The MCU instructions fall into the following five categories: * * * * * Register/memory Read-modify-write Jump/branch Bit manipulation Control 4.4.1 Register/Memory Instructions Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory using one of the addressing modes. Most register/memory instructions use the following addressing modes: * * * * * * Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Table 4-7 lists the register/memory instructions. MOTOROLA 4-12 CENTRAL PROCESSOR UNIT MC68HC705J2 Table 4-7. Register/Memory Instructions Instruction Load Accumulator from Memory Load Index Register from Memory Store Accumulator in Memory Store Index Register in Memory Add Memory to Accumulator Add Memory and Carry to Accumulator Subtract Memory Subtract Memory from Accumulator with Borrow AND Memory with Accumulator OR Memory with Accumulator Arithmetic Compare Accumulator with Memory Arithmetic Compare Index Register with Memory Bit Test Memory with Accumulator (Logical Compare) Multiply Mnemonic LDA LDX STA STX ADD ADC SUB SBC AND ORA CMP CPX BIT MUL 4.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is an exception to the read-modify-write sequence because it does not write a replacement value. Read-modify-write instructions use the following addressing modes: * * * * Inherent Direct Indexed, no offset Indexed, 8-bit offset Table 4-8 lists the read-modify-write instructions. MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-13 Table 4-8. Read-Modify-Write Instructions Instruction Increment Decrement Clear Complement Negate (Two's Complement) Rotate Left through Carry Rotate Right through Carry Logical Shift Left Logical Shift Right Arithmetic Shift Right Test for Negative or Zero Mnemonic INC DEC CLR COM NEG ROL ROR LSL LSR ASR TST 4.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Jump instructions use the following addressing modes: * * * * * Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. All branch instructions are used in the relative addressing mode. MOTOROLA 4-14 CENTRAL PROCESSOR UNIT MC68HC705J2 Bit test and branch instructions cause a branch based on the condition of any readable bit in the first 256 memory locations. These three-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the conditional branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 4-9 lists the jump and branch instructions. Table 4-9. Jump and Branch Instructions Instruction Branch Always Branch Never Branch if Bit n of M = 0 Branch if Bit n of M = 1 Branch if Higher Branch if Lower or Same Branch if Carry Clear Branch if Higher or Same Branch if Carry Set Branch if Lower Branch if Not Equal Branch if Equal Branch if Half-Carry Clear Branch if Half-Carry Set Branch if Plus Branch if Minus Branch if Interrupt Mask Clear Branch if Interrupt Mask Set Branch if Interrupt Line Low Branch if Interrupt Line High Branch to Subroutine Jump Unconditional Jump to Subroutine Mnemonic BRA BRN BRCLR BRSET BHI BLS BCC BHS BCS BLO BND BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH BSR JMP JSR MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-15 4.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory. Port register, port data direction registers, timer registers, and on-chip RAM locations are in the first 256 bytes of memory. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Bit manipulation instructions use the direct addressing mode. Table 4-10 lists these instructions. Table 4-10. Bit Manipulation Instructions Instruction Set Bit n Clear Bit n Branch if Bit n of M = 0 Branch if Bit n of M = 1 Mnemonic BSET n (n = 0 . . . 7) BCLR n (n = 0 . . . 7) BRCLR BRSET 4.4.5 Control Instructions These register reference instructions control CPU operation during program execution. Control instructions, listed in Table 4-11, use the inherent addressing mode. Table 4-11. Control Instructions Instruction Transfer Accumulator to Index Register Transfer Index Register to Accumulator Set Carry Bit Clear Carry Bit Set Interrupt Mask Clear Interrupt Mask Software Interrupt Return from Subroutine Reset Stack Pointer No Operation Stop Wait Mnemonic TAX TXA SEC CLC SEI CLI SWI RTI RSP NOP STOP WAIT MOTOROLA 4-16 CENTRAL PROCESSOR UNIT MC68HC705J2 4.4.6 Instruction Set Summary Table 4-12 is an alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Table 4-12. Instruction Set Summary Opcode Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel Operation Description HINZC Add with Carry A (A) + (M) + (C) -- IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL A9 ii B9 dd C9 hh ll D9 ee ff E9 ff F9 AB ii BB dd CB hh ll DB ee ff EB ff FB A4 ii B4 dd C4 hh ll D4 ee ff E4 ff F4 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 dd Add without Carry A (A) + (M) -- Logical AND A (A) (M) ---- -- Arithmetic Shift Left (Same as LSL) C b7 b0 0 ---- ff dd Arithmetic Shift Right b7 b0 C ---- ff Branch if Carry Bit Clear PC (PC) + 2 + rel ? C = 0 ---------- rr dd dd dd dd dd dd dd dd rr rr rr BCLR n opr Clear Bit n Mn 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- REL REL REL BCS rel BEQ rel BHCC rel Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 MC68HC705J1A Rev. 1 MOTOROLA 4-17 Cycles 2 3 4 5 4 3 2 3 4 5 4 3 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 Effect on CCR Operand Address Mode Table 4-12. Instruction Set Summary (Continued) Opcode Source Form BHCS rel BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Operation Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Description PC (PC) + 2 + rel ? H = 1 HINZC ---------- REL REL REL REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL 29 22 24 2F 2E rr rr rr rr rr PC (PC) + 2 + rel ? C Z = 0 -- -- -- -- -- PC (PC) + 2 + rel ? C = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 ---------- ---------- ---------- Bit Test Accumulator with Memory Byte (A) (M) ---- -- A5 ii B5 dd C5 hh ll D5 ee ff E5 ff F5 p 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 00 02 04 06 08 0A 0C 0E 21 rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always PC (PC) + 2 + rel ? C = 1 ---------- PC (PC) + 2 + rel ? C Z = 1 -- -- -- -- -- PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1 ---------- ---------- ---------- ---------- ---------- ---------- BRCLR n opr rel Branch if bit n clear PC (PC) + 2 + rel ? Mn = 0 -------- BRSET n opr rel Branch if Bit n Set PC (PC) + 2 + rel ? Mn = 1 -------- BRN rel Branch Never PC (PC) + 2 + rel ? 1 = 0 ---------- MOTOROLA 4-18 MC68HC705J1A Rev. 1 Cycles 3 3 3 3 3 2 3 4 5 4 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3 Effect on CCR Operand Address Mode Table 4-12. Instruction Set Summary (Continued) Opcode Source Form Operation Description Cycles 5 5 5 5 5 5 5 5 6 2 2 dd 5 3 3 6 5 2 3 4 5 4 3 5 3 3 6 5 2 3 4 5 4 3 5 3 3 6 5 2 3 4 5 4 3 Effect on CCR HINZC BSET n opr Set Bit n Mn 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd BSR rel Branch to Subroutine Clear Carry Bit Clear Interrupt Mask PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0 M $00 A $00 X $00 M $00 M $00 ---------- REL AD CLC CLI CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X -------- 0 -- 0 ------ INH INH DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX 98 9A 3F 4F 5F 6F 7F Clear Byte ---- 0 1 -- Compare Accumulator with Memory Byte (A) - (M) ---- A1 ii B1 dd C1 hh ll D1 ee ff E1 ff F1 33 43 53 63 73 dd Complement Byte (One's Complement) M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) ---- 1 Compare Index Register with Memory Byte (X) - (M) ---- 1 A3 ii B3 dd C3 hh ll D3 ee ff E3 ff F3 3A 4A 5A 6A 7A dd Decrement Byte M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 ---- -- EXCLUSIVE OR Accumulator with Memory Byte A (A) (M) ---- -- A8 ii B8 dd C8 hh ll D8 ee ff E8 ff F8 MC68HC705J1A Rev. 1 MOTOROLA 4-19 Operand rr ff ff ff Address Mode Table 4-12. Instruction Set Summary (Continued) Opcode Source Form INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X Operation Description M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 HINZC Increment Byte ---- -- DIR INH INH IX1 IX DIR EXT IX2 IX1 IX 3C 4C 5C 6C 7C dd ff Unconditional Jump PC Jump Address ---------- BC C dd C hh ll D ee ff ff C EC FC BD C dd D hh ll D ee ff ff D ED FD A6 ii B6 dd C6 hh ll D6 ee ff E6 ff F6 AE ii BE dd CE hh ll DE ee ff EE ff FE 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 ii dd Jump to Subroutine PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Conditional Address ---------- DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX Load Accumulator with Memory Byte A (M) ---- -- Load Index Register with Memory Byte X (M) ---- -- Logical Shift Left (Same as ASL) C b7 b0 0 ---- ff dd Logical Shift Right 0 b7 b0 C ---- 0 ff Unsigned Multiply X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) 0 ------ 0 11 5 3 3 6 5 Negate Byte (Two's Complement) ---- ff MOTOROLA 4-20 MC68HC705J1A Rev. 1 Cycles 5 3 3 6 5 2 3 4 3 2 5 6 7 6 5 2 3 4 5 4 3 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 Effect on CCR Operand Address Mode Table 4-12. Instruction Set Summary (Continued) Opcode Source Form NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X ROR opr RORA RORX ROR opr,X ROR ,X RSP Operation No Operation Description HINZC ---------- INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH 9D AA ii BA dd CA hh ll DA ee ff EA ff FA 39 49 59 69 79 36 46 56 66 76 9C dd Logical OR Accumulator with Memory A (A) (M) ---- -- Rotate Byte Left through Carry Bit C b7 b0 ---- ff dd Rotate Byte Right through Carry Bit C b7 b0 ---- ff Reset Stack Pointer SP $00FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) ---------- RTI Return from Interrupt INH 80 6 RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X Return from Subroutine INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX A2 ii B2 dd C2 hh ll D2 ee ff E2 ff F2 99 9B B7 dd C7 hh ll D7 ee ff E7 ff F7 8E BF dd CF hh ll DF ee ff EF ff FF 2 3 4 5 4 3 2 2 4 5 6 5 4 2 4 5 6 5 4 Subtract Memory Byte and Carry Bit from Accumulator A (A) - (M) - (C) ---- Set Carry Bit Set Interrupt Mask C1 I1 -------- 1 -- 1 ------ Store Accumulator in Memory M (A) ---- -- Stop Oscillator and Enable IRQ Pin -- 0 ------ Store Index Register In Memory M (X) ---- -- MC68HC705J1A Rev. 1 MOTOROLA 4-21 Cycles 2 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 2 Effect on CCR Operand Address Mode Table 4-12. Instruction Set Summary (Continued) Opcode Source Form SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Operation Description HINZC Subtract Memory Byte from Accumulator A (A) - (M) ---- IMM DIR EXT IX2 IX1 IX A0 ii B0 dd C0 hh ll D0 ee ff E0 ff F0 SWI Software Interrupt PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ---------- INH 83 10 TAX TST opr TSTA TSTX TST opr,X TST ,X TXA Transfer Accumulator to Index Register INH DIR INH INH IX1 IX INH 97 3D 4D 5D 6D 7D 9F dd Test Memory Byte for Negative or Zero (M) - $00 ---------- ff Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts A (X) ---------- WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n -- opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : -- ------ INH 8F 2 Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected MOTOROLA 4-22 MC68HC705J1A Rev. 1 Cycles 2 3 4 5 4 3 2 4 3 3 5 4 2 Effect on CCR Operand Address Mode MOTOROLA -23 MSB LSB Table 4-13. Opcode Map Bit Manipulation DIR DIR 0 5 Branch REL 2 5 3 Read-Modify-Write DIR 3 5 Control IX 7 6 5 Register/Memory IMM A 2 INH 4 3 INH 5 3 IX1 6 NEG IX1 1 INH 8 9 INH 9 DIR B 3 EXT C 4 IX2 D 5 IX1 E 4 IX F 3 1 BSET0 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 MSB LSB 0 1 2 3 4 5 6 7 8 9 A B C D E BRSET0 3 BRA REL 2 3 NEG DIR 1 NEGA INH 1 NEGX INH 2 NEG IX 1 RTI INH 6 2 SUB IMM 2 2 SUB DIR 3 3 SUB EXT 3 4 SUB IX2 2 5 SUB IX1 1 4 SUB IX 3 0 1 2 3 4 5 6 7 8 9 A B C D E F BRCLR0 3 BCLR0 DIR 2 5 BRN REL 3 1 11 RTS INH 2 CMP IMM 2 2 CMP DIR 3 3 CMP EXT 3 4 CMP IX2 2 5 CMP IX1 1 4 CMP IX 3 BRSET1 3 BSET1 DIR 2 5 BHI REL 3 1 5 MUL INH 3 2 3 6 5 10 SBC IMM 2 2 SBC DIR 3 3 SBC EXT 3 4 SBC IX2 2 5 SBC IX1 1 4 SBC IX 3 BRCLR1 3 BCLR1 DIR 2 5 BLS REL 2 3 COM DIR 1 5 COMA INH 1 3 COMX INH 2 3 COM IX1 1 6 COM IX 1 5 SWI INH 2 CPX IMM 2 2 CPX DIR 3 3 CPX EXT 3 4 CPX IX2 2 5 CPX IX1 1 4 CPX IX 3 BRSET2 3 BSET2 DIR 2 5 BCC REL 2 3 REL 3 LSR DIR 1 LSRA INH 1 LSRX INH 2 LSR IX1 1 LSR IX 2 AND IMM 2 2 AND DIR 3 3 AND EXT 3 4 AND IX2 2 5 AND IX1 1 4 AND IX 3 BRCLR2 3 BCLR2 BSET3 BCS/BLO 2 5 3 3 6 5 BIT IMM 2 2 BIT DIR 3 3 BIT EXT 3 4 BIT IX2 2 5 BIT IX1 1 4 BIT IX 3 DIR 2 5 DIR 2 5 BRSET3 3 BNE REL 2 3 ROR DIR 1 5 RORA INH 1 3 RORX INH 2 3 ROR IX1 1 6 ROR IX 5 2 2 LDA IMM 2 LDA DIR 3 4 LDA EXT 3 5 LDA IX2 2 6 LDA IX1 1 5 LDA IX 4 BRCLR3 3 BCLR3 DIR 2 5 BEQ REL 2 3 ASR DIR 1 5 DIR 1 5 ASRA INH 1 3 INH 1 3 ASRX INH 2 3 INH 2 3 ASR IX1 1 6 IX1 1 6 ASR IX 5 IX 5 1 TAX INH 2 2 2 STA DIR 3 3 STA EXT 3 4 STA IX2 2 5 STA IX1 1 4 STA IX 3 BRSET4 3 BSET4 DIR 2 5 BHCC BHCS ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ROL DIR 1 5 ASL/LSL 1 CLC INH 2 2 EOR IMM 2 2 EOR DIR 3 3 EOR EXT 3 4 EOR IX2 2 5 EOR IX1 1 4 EOR IX 3 REL 2 3 REL 2 3 BRCLR4 3 BCLR4 DIR 2 5 ROLA INH 1 3 ROLX INH 2 3 ROL IX1 1 6 ROL IX 5 1 SEC INH 2 2 ADC IMM 2 2 ADC DIR 3 3 ADC EXT 3 4 ADC IX2 2 5 ADC IX1 1 4 ADC IX 3 BRSET5 3 BSET5 DIR 2 5 BPL REL 2 3 DEC DIR 1 DECA INH 1 DECX INH 2 DEC IX1 1 DEC IX 1 CLI INH 2 2 ORA IMM 2 2 ORA DIR 3 3 ORA EXT 3 4 ORA IX2 2 5 ORA IX1 1 4 ORA IX 3 BRCLR5 3 BCLR5 DIR 2 5 BMI REL 3 1 5 3 3 6 5 SEI INH 2 2 ADD IMM 2 ADD DIR 3 2 ADD EXT 3 3 ADD IX2 2 4 ADD IX1 1 3 ADD IX 2 BRSET6 3 BSET6 DIR 2 5 BMC REL 2 3 INC DIR 1 4 INCA INH 1 3 INCX INH 2 3 INC IX1 1 5 INC IX 4 1 RSP INH 2 2 6 JMP DIR 3 5 JMP EXT 3 6 JMP IX2 2 7 JMP IX1 1 6 JMP IX 5 BRCLR6 3 BCLR6 DIR 2 5 BMS REL 2 3 TST DIR 1 TSTA INH 1 TSTX INH 2 TST IX1 1 TST IX 2 1 NOP INH 2 BSR REL 2 2 JSR DIR 3 3 JSR EXT 3 4 JSR IX2 2 5 JSR IX1 1 4 JSR IX 3 BRSET7 3 BSET7 DIR 2 5 BIL REL 3 1 5 3 3 6 5 STOP INH 2 2 2 LDX IMM 2 LDX DIR 3 4 LDX EXT 3 5 LDX IX2 2 6 LDX IX1 1 5 LDX IX 4 MC68HC705J1A Rev. 1.1 F BRCLR7 3 BCLR7 DIR 2 BIH REL 2 CLR DIR 1 CLRA INH 1 CLRX INH 2 CLR IX1 1 CLR IX 1 WAIT INH 1 TXA INH 2 STX DIR 3 STX EXT 3 STX IX2 2 STX IX1 1 STX IX INH = Inherent IMM = Immediate DIR = Direct EXT = Extended REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset MSB LSB LSB of Opcode in Hexadecimal 0 3 0 MSB of Opcode in Hexadecimal 5 Number of Cycles BRSET0 Opcode Mnemonic DIR Number of Bytes/Addressing Mode 4.5 Low-Power Modes The following paragraphs describe the STOP and WAIT modes. (Refer also to 6.2Data Retention Mode.) 4.5.1 STOP Mode The STOP instruction puts the MCU in its lowest power-consumption mode. In STOP mode, the following events occur: * The CPU clears TOF and RTIF, the timer interrupt flags in the timer control and status register, removing any pending timer interrupts. * The CPU clears TOIE and RTIE, the timer interrupt enable bits in the timer control and status register, disabling further timer interrupts. * The CPU clears the divide-by-four timer prescaler. * The CPU clears the interrupt mask in the condition code register, enabling external interrupts. * The internal oscillator stops, halting all internal processing, including operation of the timer and the COP timer. The STOP instruction does not affect any other registers or any I/O lines. The following conditions bring the MCU out of STOP mode: * An external interrupt. An external interrupt automatically loads the program counter with the contents of locations $0FFA and $0FFB, the locations of the vector address of the external interrupt service routine. * A reset signal on the RESET pin. A reset automatically loads the program counter with the contents of locations $0FFE and $0FFF, the locations of the vector address of the reset service routine. Refer to Figure 10-7 in SECTION 10 ELECTRICAL SPECIFICATIONS for STOP recovery timing. MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-23 Figure 4-2 shows the sequence of events caused by the STOP instruction. STOP CLEAR TIMER INTERRUPT FLAGS TIMER INTERRUPT ENABLE BIT CLEAR TIMER PRESCALER. CLEAR CCR INTERRUPT MASK STOP OSCILLATOR. NO RESET ? YES NO EXTERNAL INTERRUPT ? YES TURN ON OSCILLATO DELAY 4064 CYCLE TO STABILIZE. (1) FETCH RESET VECTOR or (2) SERVICE INTERRUPT. a. SAVE CPU REGISTERS ON S b. SET CCR INTERRUPT MASK. c. VECTOR TO INTERRUPT SERVICE ROUTINE. Figure 4-2. STOP Instruction Flowchart MOTOROLA 4-24 CENTRAL PROCESSOR UNIT MC68HC705J2 4.5.2 WAIT Mode The WAIT instruction puts the MCU in an intermediate power-consumption mode. In WAIT mode, the following events occur: * All CPU clocks stop. * The CPU clears the interrupt mask in the condition code register, enabling external interrupts and timer interrupts. The WAIT instruction does not affect any other registers or any I/O lines. The timer and COP timer remain active in WAIT mode. The following conditions bring the MCU out of WAIT mode: * A timer interrupt. If a real-time interrupt or a timer overflow interrupt occurs during WAIT mode, the MCU loads the program counter with the contents of locations $0FF8 and $0FF9, the locations of the vector address of the timer interrupt service routine. * An external interrupt. An external interrupt automatically loads the program counter with the contents of locations $0FFA and $0FFB, the locations of the vector address of the external interrupt service routine. * A COP timer reset. A timeout of the COP timer during WAIT mode resets the MCU. The programmer can enable real-time interrupts so the MCU can periodically exit WAIT mode to reset the COP timer. * A reset signal on the RESET pin during WAIT mode resets the MCU. A COP timer reset or a reset signal on the RESET pin automatically loads the program counter with the contents of locations $0FFE and $0FFF, the locations of the vector address of the reset service routine. Figure 4-3 shows the sequence of events caused by the WAIT instruction. MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-25 WAIT OSCILLATOR ACTIVE. TIMER CLOCKS ACTIVE. STOP CPU CLOCKS. CLEAR CCR INTERRUPT MA RESET ? YES NO EXTERNAL INTERRUPT ? YES YES NO INTERNAL TIMER INTERRUPT ? NO RESTART CPU CLOCK. (1) FETCH RESET VECTOR o (2) SERVICE INTERRUPT. a. SAVE CPU REGS ON S b. SET I-BIT IN CCR. c. VECTOR TO INTERRUP SERVICE ROUTINE. Figure 4-3. WAIT Instruction Flowchart MOTOROLA 4-26 CENTRAL PROCESSOR UNIT MC68HC705J2 SECTION 5 RESETS AND INTERRUPTS This section describes how resets reinitialize the MCU and how interrupts temporarily change the normal processing sequence. 5.1 Resets A reset immediately stops the operation of the instruction being executed. A reset initializes certain control bits to known conditions and loads the program counter with a user-defined reset vector address. The following conditions produce a reset: * * * * Initial power-up (power-on reset) A logical zero applied to the RESET pin (external reset) Timeout of the COP timer (COP reset) An opcode fetch from an address not in the memory map (illegal address reset) A reset does the following things to reinitialize the MCU: * Clears all implemented data direction register bits so that the corresponding I/O pins are inputs * Loads the stack pointer with $FF * Sets the interrupt mask, inhibiting interrupts * Clears the TOFE and RTIE bits in the timer control and status register * Clears the STOP latch, enabling the CPU clocks * Clears the WAIT latch, waking the CPU from the WAIT mode * Loads the program counter with the user-defined reset vector 5.1.1 Power-On Reset A positive transition on the VDD pin generates a power-on reset. The power-on reset is strictly for power-up conditions and cannot be used to detect drops in power supply voltage. MC68HC705J2 RESETS AND INTERRUPTS MOTOROLA 5-1 A 4064 tcyc (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. If the RESET pin is at a logical zero at the end of 4064 tcyc, the MCU remains in the reset condition until the signal on the RESET pin goes to a logical one. 5.1.2 External Reset t A zero applied to the RESET pin for one and one-half cyc generates an external reset. A Schmitt trigger senses the logic level at the RESET pin. 5.1.3 Computer Operating Properly (COP) Reset A timeout of the COP timer generates a COP reset. The COP timer is part of a software error detection system and must be cleared periodically to start a new timeout period. (See 7.3 COP Timer.) To clear the COP timer and prevent a COP reset, write a zero to bit 0 (COPR) of the COP control register at location $0FF0 before the COP timer times out. The COP control register is a write-only register that returns the contents of an EPROM location when read. See Figure 5-1. COPR -- COP Control Register Bit 7 -- RESET -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 -- -- Bit 0 COPR 0 $0FF0 Figure 5-1. COP Control Register COPR -- COP Reset COPR is a write-only bit. Periodically writing a zero to COPR prevents the COP timer from resetting the MCU. 5.1.4 Illegal Address Reset An opcode fetch from an address that is not in the EPROM (locations $0700- $0EFF), or the RAM ($0090-$00FF) generates an illegal address reset. MOTOROLA 5-2 RESETS AND INTERRUPTS MC68HC705J2 5.2 Interrupts An interrupt temporarily stops normal processing to process a particular event. Unlike a reset, an interrupt does not stop the operation of the instruction being executed. An interrupt takes effect when the current instruction completes its execution. An interrupt saves the CPU registers on the stack and loads the program counter with a user-defined interrupt vector address. The following conditions produce an interrupt: * Timer overflow or real-time interrupt request (timer interrupts) * A logical zero applied to the IRQ pin (external interrupt) * SWI instruction (software interrupt) The CPU does the following things to begin servicing an interrupt: * Stores the contents of the CPU registers on the stack as shown in Figure 5-2 TOWARD LOWER ADDRESSES (LOWEST STACK ADDRESS IS $0 STACK 7 CONDITION CODE REGIST INTERRUPT ACCUMULATOR INDEX REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW UNSTACK TOWARD HIGHER ADDRESSES (HIGHEST STACK ADDRESS IS $00 RETURN 0 Figure 5-2. Interrupt Stacking Order * Sets the interrupt mask to prevent further interrupts * Loads the program counter with the contents of the appropriate interrupt vector locations: -- $0FF8 and $0FF9 (timer interrupt vector) -- $0FFA and $0FFB (external interrupt vector) -- $0FFC and $0FFD (software interrupt vector) MC68HC705J2 RESETS AND INTERRUPTS MOTOROLA 5-3 The return from interrupt (RTI) instruction causes the CPU to recover the CPU registers from the stack as shown in Figure 5-2. 5.2.1 Timer Interrupts The timer generates two kinds of interrupts: * Timer overflow interrupt * Real-time interrupt Setting the interrupt mask in the condition code register disables timer interrupts. 5.2.1.1 Timer Overflow Interrupts A timer overflow interrupt occurs if the timer overflow flag, TOF, becomes set while the timer overflow interrupt enable bit, TOIE, is also set. TOF and TOIE are in the timer control and status register. See 7.2 Timer Control a n d Status Register. 5.2.1.2 Real-Time Interrupts A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set while the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in the timer control and status register. See 7.2 Timer Control and Status Register. 5.2.2 External Interrupt When a falling edge occurs on the IRQ pin, an external interrupt request is latched. When the CPU completes its current instruction, it tests the external interrupt latch. If the interrupt latch is set and the interrupt mask in the condition code register is reset, the CPU then begins the interrupt sequence. The CPU clears the interrupt latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. As soon as the interrupt mask is cleared (usually during the return from interrupt), the CPU can recognize the new interrupt request. Figure 5-3 shows the sequence of events caused by an interrupt. MOTOROLA 5-4 RESETS AND INTERRUPTS MC68HC705J2 FROM RESET YES INTERRUPT MASK SET ? NO CLEAR IRQ REQUEST LATCH. EXTERNAL INTERRUPT ? NO YES TIMER INTERRUPT ? NO YES STACK PCL, PCH, X, A, CCR SET INTERRUPT MASK. LOAD PC WITH VECTOR: MC68HC705J2 NATIVE MOD TIMER: $0FF8, $0FF9 EXTERNAL: $0FFA, $0FFB SOFTWARE: $0FFC, $0FFD MC68HC05J1 EMULATION M TIMER: $07F8, $07F9 EXTERNAL: $07FA, $07FB SOFTWARE: $07FC, $07FD FETCH NEXT INSTRUCTION. SWI INSTRUCTION ? NO RTI INSTRUCTION ? NO YES YES RESTORE REGISTERS FROM STACK CCR, A, X, PCH, PCL EXECUTE INSTRUCTION. Figure 5-3. Interrupt Flowchart MC68HC705J2 RESETS AND INTERRUPTS MOTOROLA 5-5 Either an edge-sensitive or an edge- and level-sensitive external interrupt trigger is programmable in the mask option register. Figure 5-4 shows the internal logic of this programmable option. LEVEL SENSITIVE TRIGG (MOR OPTIO VDD INTERRUPT MAS EXTERNAL INTERRUPT REQUEST D IRQ C Q Q R RESET EXTERNAL INTERRUP BEING SERVICED (VECTOR FETCH) Figure 5-4. External Interrupt Trigger Option The edge- and level-sensitive trigger option allows multiple external interrupt sources to be wire-ORed to the IRQ pin. With the level-sensitive trigger option, an external interrupt request is latched as long as any source is holding the IRQ pin low. Setting the interrupt mask in the condition code register disables external interrupts. 5.2.3 Software Interrupt The software interrupt (SWI) instruction causes a nonmaskable interrupt. MOTOROLA 5-6 RESETS AND INTERRUPTS MC68HC705J2 SECTION 6 MEMORY This section describes the organization of the on-chip memory. 6.1 Memory Map The CPU can address 4 Kbytes of memory space. The program counter normally advances one address at a time through the memory, reading the program instructions and data. The EPROM portion of memory holds the program instructions, fixed data, user-defined vectors, and service routines. The RAM portion of memory holds variable data. I/O registers are memory-mapped so that the CPU can access their locations in the same way that it accesses all other memory locations. Figure 6-1 is a memory map of the MCU. Figure 6-2 is a more detailed memory map of the 32-byte I/O register section. 6.1.1 Input/Output Section The first 32 addresses of the memory space, $0000-$001F, are defined as the I/O section. These are the addresses of the I/O control registers, I/O status registers, and I/O data registers. 6.1.2 RAM The MCU has 112 bytes of fully static read/write memory for storage of variable and temporary data during program execution. RAM addresses $00C0-$00FF serve as the stack. The CPU uses the stack to save CPU register contents before processing an interrupt or subroutine call. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful if using the stack addresses ($00C0-$00FF) for data storage or as a temporary work area. The CPU may overwrite data in the stack during a subroutine or interrupt. MC68HC705J2 MEMORY MOTOROLA 6-1 $000 $001F $002 $008F $009 I/O REGISTERS 32 BYTES UNUSED 112 BYTES $00BF $00C SRAM 112 BYTE STACK 64 BYTES $00FF $010 UNUSED 1536 BYTES $06FF $070 PORT A DATA REGIST PORT B DATA REGIST UNUSED UNUSED PORT A DATA DIRECTION REGI PORT B DATA DIRECTION REGIS UNUSED UNUSED TIMER CONTROL AND STATUS REG TIMER COUNTER REGISTE UNUSED * * * UNUSED EPROM PROGRAMMING REGIST UNUSED UNUSED RESERVED $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A * * * $001B $001C $001D $001E $001F USER EPROM 2048 BYTES $0EFF $0F00 $0F0 MASK OPTION REGIST COP REGISTE* USER EPROM 8 BYTES TIMER INTERRUPT VECTOR (H TIMER INTERRUPT VECTOR ( EXTERNAL INTERRUPT VECTOR EXTERNAL INTERRUPT VECTOR SOFTWARE INTERRUPT VECTOR SOFTWARE INTERRUPT VECTOR RESET VECTOR (HI RESET VECTOR (LO WRITING 0 TO BIT 0 OF $0FF0 C *COP TIMER. READING $0FF0 RET USER EPROM DATA. $0FF0 * * * $0FF7 $0FF8 $0FF9 $0FFA $0FFB $0FFC $0FFD $0FFE $0FFF BOOTLOADER RO 239 BYTES $0FEF $0FF0 USER VECTOR (EPROM) 16 BYTES $0FFF Figure 6-1. Memory Map MOTOROLA 6-2 MEMORY MC68HC705J2 Bit 7 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C * * * $0019 $001A $001B $001C $001D $001E $001F $0F00 $0FF0 -- -- -- 0 -- -- -- -- PA7 0 -- -- DDRA7 0 -- -- TOF Bit 7 -- -- -- 6 PA6 0 -- -- DDRA6 0 -- -- RTIF 6 -- -- -- 5 PA5 PB5 -- -- DDRA5 DDRB5 -- -- TOIE 5 -- -- -- 4 PA4 PB4 -- -- DDRA4 DDRB4 -- -- RTIE 4 -- -- -- 3 PA3 PB3 -- -- DDRA3 DDRB3 -- -- 0 3 -- -- -- 2 PA2 PB2 -- -- DDRA2 DDRB2 -- -- 0 2 -- -- -- 1 PA1 PB1 -- -- DDRA1 DDRB1 -- -- RT1 1 -- -- -- Bit 0 PA0 PB0 -- -- DDRA0 DDRB0 -- -- RT0 Bit 0 -- -- -- PORTA PORTB UNUSED UNUSED DDRA DDRB UNUSED UNUSED TCSR TCR UNUSED UNUSED UNUSED * * * -- -- -- 0 -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- LATCH -- -- -- J1 -- -- -- 0 -- -- -- IRQ -- -- -- EPGM -- -- -- COP COPR UNUSED UNUSED UNUSED PROG UNUSED UNUSED RESERVED MOR COP Figure 6-2. I/O Registers MC68HC705J2 MEMORY MOTOROLA 6-3 6.1.3 EPROM Two Kbytes of user EPROM for storage of program instructions and fixed data are located at addresses $0700-$0EFF. The eight addresses from $0FF8- $0FFF are EPROM locations reserved for interrupt vectors and reset vectors. Eight additional EPROM bytes are located at $0FF0-$0FF8. There are two ways to write data to the EPROM: * The EPROM programming register contains the control bits for programming the EPROM on a byte-by-byte basis. * The bootloader ROM contains routines to download the contents of an external memory device to the on-chip EPROM. 6.1.3.1 EPROM Programming The EPROM programming register, shown in Figure 6-3, contains the control bits for programming the EPROM. PROG -- EPROM Programming Register Bit 7 0 RESET 0 6 0 0 5 0 0 4 0 0 3 0 0 2 LATCH 0 1 0 0 Bit 0 EPGM 0 $001C Figure 6-3. EPROM Programming Register (PROG) LATCH -- EPROM Bus Latch This read/write bit causes address and data buses to be latched for EPROM programming. Clearing the LATCH bit automatically clears the EPGM bit. 1 = Address and data buses configured for EPROM programming 0 = Address and data buses configured for normal operation EPGM -- EPROM Programming This read/write bit applies programming power to the EPROM. To write the EPGM bit, the LATCH bit must already be set. 1 = EPROM programming power switched on 0 = EPROM programming power switched off Bits 7-3 and 1 -- Not used; always read as zeros. MOTOROLA 6-4 MEMORY MC68HC705J2 Take the following steps to program a byte of EPROM: 1. 2. 3. 4. 5. Apply 16.5 V to the IRQ /VPP pin. Set the LATCH bit. Write to any EPROM address. Set the EPGM bit for a time tEPGM to apply the programming voltage. Clear the LATCH bit. 6.1.3.2 EPROM Erasing The erased state of an EPROM bit is zero. Erase the EPROM by exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet light source 1 inch from the EPROM. Do not use a shortwave filter. NOTE Windowed packages must have the window covered during programming and operation. 6.1.4 Bootloader ROM Addresses $0F01-$0FEF contain the bootloader ROM, which can copy and verify the contents of an external EPROM to the on-chip EPROM. See SECTION 8 BOOTLOADER MODE. MC68HC705J2 MEMORY MOTOROLA 6-5 6.2 Data Retention Mode In data retention mode, the MCU retains RAM contents and CPU register contents at VDD voltages as low as 2.0 Vdc. The data-retention feature allows the MCU to remain in a low power-consumption state during which it retains data, but the CPU cannot execute instructions. To put the MCU in data retention mode: 1. Drive the RESET pin to zero. 2. Lower the VDD voltage. The RESET line must remain low continuously during data retention mode. To take the MCU out of data retention mode: 1. Return VDD to normal operating voltage. 2. Return the RESET pin to logical one. MOTOROLA 6-6 MEMORY MC68HC705J2 SECTION 7 TIMER This section describes the operation of the timer and the COP timer. Figure 7-1 shows the organization of the timer system. INTERNAL PROCESSO CLOCK / (XTAL 2) LEAST SIGNIFICANT EIGHT BITS OF 15-STAGE RIPPLE /2 MSB /2 /2 /2 /2 /2 /2 LSB /2 FIXED DIVIDE BY 4 TIMER COUNTER REGISTE TCR $000 INTERRUPT CIRCU TOFE RTIE RTIF TOF INTERRUPT REQUES 0 0 TIMER CONTROL AND STATUS REG RT1 RT0 TCSR $00 RTI RATE SELEC POWER-ON RESET (PO /2 /2 /2 /2 /2 /2 /2 MOST SIGNIFICANT SEVEN BITS OF 15-STAGE RIPPLE /2 CLEAR COP TIME /2 /2 S R Q COP TIMER RESE Figure 7-1. Timer MC68HC705J2 TIMER MOTOROLA 7-1 7.1 Timer Counter Register (TCR) A 15-stage ripple counter is the core of the timer. The value of the first eight stages is readable at any time from the read-only timer counter register shown in Figure 7-2. TCR -- Timer Counter Register Bit 7 RESET 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 $0009 Figure 7-2. Timer Counter Register (TCR) Power-on clears the entire counter chain and begins clocking the counter. After 4064 cycles of the internal clock, the power-on reset circuit is released, clearing the counter again and allowing the MCU to come out of reset. A timer overflow function at the eighth counter stage makes timer interrupts possible every 1024 internal clock cycles. 7.2 Timer Control and Status Register (TCSR) Timer interrupt flags, timer interrupt enable bits, and real-time interrupt rate select bits are in the read/write timer control and status register. TCSR -- Timer Control and Status Register Bit 7 TOF RESET 0 6 RTIF 0 5 TOIE 0 4 RTIE 0 3 0 0 2 0 0 1 RT1 1 Bit 0 RT0 1 $0008 Figure 7-3. Timer Control and Status Register (TCSR) MOTOROLA 7-2 TIMER MC68HC705J2 TOF -- Timer Overflow Flag This clearable, read-only bit becomes set when the first eight stages of the counter roll over from $FF to $00. TOF generates a timer overflow interrupt request if TOFE is also set. Clear TOF by writing a zero to it. Writing a one to TOF has no effect. RTIF -- Real-Time Interrupt Flag This clearable, read-only bit becomes set when the selected RTI output becomes active. RTIF generates a real-time interrupt request if RTIE is also set. Clear RTIF by writing a zero to it. Writing a one to RTIF has no effect. TOIE -- Timer Overflow Interrupt Enable This read/write bit enables timer overflow interrupts. 1 = Timer overflow interrupts enabled 0 = Timer overflow interrupts disabled RTIE -- Real-Time Interrupt Enable This read/write bit enables real-time interrupts 1 = Real-time interrupts enabled 0 = Real-time interrupts disabled Bits 3 and 2 -- Not used. Always read as zeros. RT1, RT0 -- Real-Time 1 and 0 These read/write bits select one of four real-time interrupt rates. See Table 7-1. The real-time interrupt rate should be selected by reset initialization software. A reset sets both RT1 and RT0, selecting the lowest real-time interrupt rate. Changing the real-time interrupt rate near the end of the RTI period or during a cycle in which the counter is switching can produce unpredictable results. Because the selected RTI output drives the COP timer, changing the real-time interrupt rate also changes the counting rate of the COP timer. Table 7-1. Real-Time Interrupt Rate Selection RT1:RT0 00 01 10 11 RTI Rate RTI Period (f o p = 2 MHz) 8.2 ms 16.4 ms 32.8 ms 65.5 ms COP Timeout Period (-0/+1 RTI Period) 7 x RTI Period 7 x RTI Period 7 x RTI Period 7 x RTI Period Minimum COP Timeout Period ( fo p = 2 MHz) 57.3 ms 114.7 ms 229.4 ms 458.8 ms fop / 214 fop / 215 fop / 216 fop / 217 MC68HC705J2 TIMER MOTOROLA 7-3 7.3 COP Timer Three counter stages at the end of the timer make up the computer operating properly (COP) timer. (See Figure 7-1.) The COP timer is a software error detection system that automatically times out and resets the MCU if not cleared periodically by a program sequence. Writing a zero to bit 0 of the COP register clears the COP timer and prevents a COP timer reset. (See Figure 7-4.) COPR -- COP Register $0FF0 MC68HC05J1 Emulation Mode: $ 0 7 F 0 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 -- -- Bit 0 COPC 0 Bit 7 -- RESET -- 6 -- -- Figure 7-4. COP Register (COPR) COPC -- COP Clear This write-only bit resets the COP timer. Reading address $0FF0 returns the EPROM data at that address. MOTOROLA 7-4 TIMER MC68HC705J2 SECTION 8 BOOTLOADER MODE This section describes how to use the bootloader ROM to download to the on-chip EPROM. 8.1 Bootloader ROM The bootloader ROM, located at addresses $0F01-$0FEF, contains routines for copying to the on-chip EPROM from an external EPROM or from a personal computer. In MC68HC705J2 native mode, the bootloader copies to the 2 Kbyte space located at EPROM addresses $0700-$0EFF. In MC68HC05J1 emulation mode, the bootloader copies to the 1 Kbyte space located at EPROM addresses $0300-$06FF. The addresses of the copied code must correspond to the internal addresses to which the code is copied. The bootloader ignores all other addresses. The COP timer is automatically disabled in bootloader mode. 8.1.1 External EPROM Downloading Figure 8-1 shows the circuit used to download to the on-chip EPROM from a 2764 EPROM. The bootloader circuit includes an external 12-bit counter to address the EPROM containing the code to be copied. Operation is fastest when unused external EPROM addresses contain $00. MC68HC705J2 BOOTLOADER MODE MOTOROLA 8-1 MC68JC705 VPP 4 MHz 19 1 IRQ/V PP OSC1 PA0 18 PA1 17 PA2 16 15 PA3 PA4 14 PA5 13 PA6 12 11 PA7 D0 D1 D2 D3 D4 D5 D6 D7 CE OE 2764 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 10 k MC14040 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 RST CLK 2 OSC2 10 M 15 pF 15 pF VDD S1 10 k 20 RESET 1F 8 VDD 7 PROGRAM VDD VDD 9 PB0 4 PB4 3 PB5 VDD 10 k 10 k 1 2 3 PB1 PB2 6 S2 330 VERIFY VSS 10 5 PB3 CONNECT 2 AND 3 FOR MC68HC705J2 NATIVE MO CONNECT 1 AND 2 FOR MC68HC05J1 EMULATION M 330 Figure 8-1. Bootloader Circuit The bootloader function begins when a rising edge occurs on the RESET pin while the IRQ /VPP pin is at VPP, the PB1 pin is at logical one, and the PB0 pin is grounded. The PB2 pin selects the bootloader function, as the following table shows. Table 8-1. Bootloader Function Selection PB2 1 0 Verify Bootloader Function Program and Verify MOTOROLA 8-2 BOOTLOADER MODE MC68HC705J2 Complete the following steps to bootload the MCU: 1. Turn off all power to the circuit. 2. Install the MCU and the EPROM. 3. Select the MCU mode: a. Install a jumper between points 2 and 3 to program the MCU as an MC68HC705J2. b. Install a jumper between points 1 and 2 to program the MCU as an MC68HC05J1. 4. Select the bootloader function: a. Open switch S2 to select the program and verify function. b. Close switch S2 to select the verify only function. 5. Close switch S1 to reset the MCU. 6. Apply VDD to the circuit. 7. Apply the EPROM programming voltage, VPP, to the circuit. 8. Open switch S1 to take the MCU out of reset. During programming the PROGRAM LED turns on. It turns off when the verification routine begins. If verification is successful, the VERIFY LED turns on. If the bootloader finds an error during verification, it puts the error address on the external address bus and stops running. 9. Close switch S1 to reset the MCU. 10. Remove the VPP voltage. 11. Remove the VDD voltage. 8.2 Host Downloading The MC68HC05P8EVS board supports downloading user programs directly from a personal computer. Refer to MC68HC05P8EVS Customer Specified Integrated Circuit (CSIC) Evaluation System, Motorola document number BR735/D. MC68HC705J2 BOOTLOADER MODE MOTOROLA 8-3 8.3 Mask Option Register (MOR) The mask option register is an EPROM byte that contains three bits to control the following options: * MC68HC05J1 emulation mode * External interrupt trigger sensitivity * COP timer (enable/disable) The mask option register is programmable only when using the bootloader function to download to the EPROM. MOR -- Mask Option Register $0F00 MC68HC05J1 Emulation Mode: $ 0 7 0 0 4 -- 3 -- 2 J1 1 IRQ Bit 0 COP Bit 7 -- 6 -- 5 -- Figure 8-2. Mask Option Register (MOR) J1 -- MC68HC05J1 Emulation Mode Select This bit can be read at any time, but can be programmed only by the bootloader. 1 = Emulation mode selected; MCU functions as MC68HC05J1 0 = (Erased state) MC68HC705J2 native mode selected IRQ -- Interrupt Request This bit can be read at any time, but can be programmed only by the bootloader. 1 = IRQ trigger is both edge-sensitive and level-sensitive 0 = (Erased state) IRQ trigger is edge-sensitive only COP -- COP Timer Enable This bit can be read at any time, but can be programmed only by the bootloader. 1 = COP timer enabled 0 = (Erased state) COP timer disabled MOTOROLA 8-4 BOOTLOADER MODE MC68HC705J2 SECTION 9 MC68HC05J1 EMULATION MODE This section describes how to use the MC68HC05J1 emulation mode to achieve compatibility with MC68HC05J1 devices. 9.1 Bootloading Use the bootloader function to put the MCU in MC68HC05J1 emulation mode. To activate the emulation mode: 1. Connect pin PB5 to VDD in the bootloader circuit. 2. Program the J1 bit (in the mask option register) high. 9.2 MC68HC05J1 Emulation In MC68HC05J1 emulation mode, the MCU operates as an MC68HC05J1 with the following exceptions: * The emulation mode does not support the RC oscillator mask option of the MC68HC05J1. * The emulation mode does not support the STOP disable mask option of the MC68HC05J1. * The emulation mode has no self-check function. MC68HC705J2 MC68HC05J1 EMULATION MODE MOTOROLA 9-1 9.3 Memory Map Figure 9-1 shows the 2 Kbyte MC68HC05J1 emulation mode memory map. $000 $001F $002 I/O REGISTERS 32 BYTES UNUSED 160 BYTES $00BF $00C STACK RAM 64 BYTES $00FF $010 UNUSED 512 BYTES $02FF $030 PORT A DATA REGIST PORT B DATA REGIST UNUSED UNUSED PORT A DATA DIRECTION REGI PORT B DATA DIRECTION REGIS UNUSED UNUSED TIMER CONTROL & STATUS REGI TIMER COUNTER REGISTE UNUSED * * * UNUSED EPROM PROGRAMMING REGIST UNUSED UNUSED RESERVED $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A * * * $001B $001C $001D $001E $001F USER EPROM 1024 BYTES $06FF $070 $070 MASK OPTION REGIST COP REGISTE* USER EPROM 8 BYTES TIMER INTERRUPT VECTOR (H TIMER INTERRUPT VECTOR ( EXTERNAL INTERRUPT VECTOR EXTERNAL INTERRUPT VECTOR SOFTWARE INTERRUPT VECTOR SOFTWARE INTERRUPT VECTOR RESET VECTOR (HI RESET VECTOR (LO $07F0 * * * $07F7 $07F8 $07F9 $07FA $07FB $07FC $07FD $07FE $07FF BOOTLOADER RO 239 BYTES $07EF $07F0 USER VECTOR (EPROM) 16 BYTES $07FF *WRITING 0 TO BIT 0 OF $07F0 C COP TIMER. READING $07F0 RET USER EPROM DATA. Figure 9-1. MC68HC05J1 Emulation Mode Memory Map MOTOROLA 9-2 MC68HC05J1 EMULATION MODE MC68HC705J2 SECTION 10 ELECTRICAL SPECIFICATIONS This section contains parametric and timing information. 10.1 Maximum Ratings The MCU contains circuitry that protects the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in Table 10-1. Keep Vin and Vout within the range VSS (Vin or Vout) VDD. Connect unused inputs to the appropriate logical voltage level, either VSS or VDD. Table 10-1. Maximum Ratings Rating Supply Voltage Input Voltage All Pins in Normal Operation IRQ /VPP Pin in Bootloader Mode EPROM Programming Voltage (IRQ /VPP Pin) Current Drain Per Pin (ExcludingVDD and VSS) Operating Temperature Range MC68HC705J2P, DW (Standard) MC68HC705J2CP, CDW (Extended) MC68HC705J2VP , VDW Storage Temperature Range Symbol VDD Vin VPP I TA Value -0.3 to +7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to 2 x VDD + 0.3 16.75 25 0 to +70 -40 to +85 -40 to +105 -65 to +150 Unit V V V mA C C TSTG 10.2 Thermal Characteristics Table 10-2. Thermal Resistance Characteristic Thermal Resistance PDIP SOIC Symbol J A Value 60 60 Unit C/W MC68HC705J2 ELECTRICAL SPECIFICATIONS MOTOROLA 10-1 10.3 Power Considerations The average chip-junction temperature, TJ, in C, can be obtained from: TJ = TA + (PD x JA) where: TA = Ambient temperature, C JA = Package thermal resistance, junction to ambient, C/W PD = PINT + PI/O PINT = IDD x VDD watts (chip internal power) PI/O = Power dissipation on input and output pins (user-determined) For most applications PI/O PINT and can be neglected. The following is an approximate relationship between PD and TJ (neglecting PI/O): PD = K / (TJ + 273 C) Solving equations (1) and (2) for K gives: K = PD x (TA + 273 C) + JA x (PD)2 (3) (2) (1) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. MOTOROLA 10-2 ELECTRICAL SPECIFICATIONS MC68HC705J2 10.4 DC Electrical Characteristics (VDD = 5.0 Vdc) Table 10-3. DC Electrical Characteristics (VD D = 5.0 Vdc) Characteristic Output Voltage Iload = 10.0 A Iload = -10.0 A Output High Voltage (Iload = -0.8 mA) PA7-PA0, PB5-PB0 Output Low Voltage (Iload = 1.6 mA) PA7-PA0, PB5-PB0 Input High Voltage PA7-PA0, PB5-PB0, IRQ /VPP, RESET , OSC1 Input Low Voltage PA7-PA0, PB5-PB0, IRQ /VPP, RESET , OSC1 Supply Current (See NOTES.) Run Wait Stop 25 C -40 to +85 C I/O Ports High-Z Leakage Current PA7-PA0, PB5-PB0 Input Current RESET , IRQ /VPP, OSC1 Capacitance Ports (as input or output) RESET , IRQ /VPP Programming Voltage Programming Current Programming Time/Byte NOTES: 1. Typical values at midpoint of voltage range, 25 C only. 2. Run (operating) IDD and wait IDD measured using external square wave clock source (fosc = 4.2 MHz), all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. 3. Wait IDD and Stop IDD: all ports configured as inputs; VIL = 0.2 V, VIH = VDD - 0.2 V. 4. Stop IDD measured with OSC1 = VSS. 5. Standard temperature range is 0 C to 70 C. 6. OSC2 capacitance linearly affects Wait IDD . 7. Programming voltage measured at IRQ/VPP pin. Symbol VOL VOH VOH VOL VIH VIL Min -- VDD - 0.1 VDD - 0.8 -- 0.7 x VDD VSS -- -- -- -- IOZ Iin -- -- -- -- 16.25 -- 4 Typ -- -- -- -- -- -- 5.0 1.3 2.0 -- -- -- -- -- 16.5 5 -- Max 0.1 -- -- 0.4 VDD 0.2 x VDD 7.0 2.5 30 100 10 1 12 8 16.75 10 -- Unit V V V V V mA mA A A A A pF V mA ms IDD Cout Cin VPP IP P tEPGM MC68HC705J2 ELECTRICAL SPECIFICATIONS MOTOROLA 10-3 10.5 DC Electrical Characteristics (VDD = 3.3 Vdc) Table 10-4. DC Electrical Characteristics (VD D = 3.3 Vdc) Characteristic Output Voltage Iload = 10.0 A Iload = -10.0 A Output High Voltage (Iload = -0.2 mA) PA7-PA0, PB5-PB0 Output Low Voltage (Iload = 0.4 mA) PA7-PA0, PB5-PB0 Input High Voltage PA7-PA0, PB5-PB0, IRQ /VPP, RESET , OSC1 Input Low Voltage PA7-PA0, PB5-PB0, IRQ /VPP, RESET , OSC1 Supply Current (See NOTES.) Run Wait Stop 25 C -40 to +85 C I/O Ports High-Z Leakage Current PA7-PA0, PB5-PB0 Input Current RESET , IRQ /VPP, OSC1 Capacitance Ports (as input or output) RESET , IRQ /VPP NOTES: 1. Typical values at midpoint of voltage range, 25 C only. 2. Run (operating) IDD and Wait IDD measured using external square wave clock source (fosc = 2 MHz), all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. 3. Wait IDD and Stop IDD: all ports configured as inputs; VIL = 0.2 V, VIH = VDD - 0.2 V. 4. Stop IDD measured with OSC1 = VSS. 5. Standard temperature range is 0 C to 70 C. 6. OSC2 capacitance linearly affects Wait IDD . Symbol VOL VOH VOH VOL VIH VIL Min -- VDD - 0.1 VDD - 0.3 -- 0.7 x VDD VSS -- -- -- -- Ioz Iin Cout Cin -- -- -- -- Typ -- -- -- -- -- -- 1.3 0.7 1.0 -- -- -- -- -- Max 0.1 -- -- 0.3 VDD 0.2 x VDD 2.0 1.0 20 50 10 1 12 8 Unit V V V V V IDD mA mA A A A A pF pF VDD R2 TEST POIN PA7-PA0, PB5-P C R1 PINS VDD R1 R2 C 50 pF 50 pF 4.5 V 3.26 k 2.38 k 3.0 V 10.91 k 6.32 k MOTOROLA 10-4 ELECTRICAL SPECIFICATIONS MC68HC705J2 Figure 10-2. Typical High-Side Driver Characteristics NO EN OT TE E1 25 ) 3 C NO MI NA LP RO CE SS ING -4 0 C ( E SE 1) 300 m 250 m VOL 200 m 150 m 100 m 50 m 0 0 85 300 m 250 m VOL NO M IN AL SE E 350 m PR O CE SS IN G 400 m 400 m 350 m NO T E (SE (S EE C C -4 C 0 (SE O EN 150 m 100 m VDD = 5.0 2.0 mA 4.0 mA 6.0 mA IOL 8.0 mA 10.0 m 85 C 25 NOTES: 1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances. Within the limited range of values shown, V vs I curves are approximately straight lines. 2. At V DD= 5.0 V, devices are specified and tested for V 400 mV @ I =OL mA. 1.6 OL 3. At V DD= 3.3 V, devices are specified and tested for V 300 mV @ I =OL mA. 0.4 OL Figure 10-3. Typical Low-Side Driver Characteristics E SE TE NO 2 TE 1) 200 m NO TE 1) 50 m 0 0 2.0 mA VDD = 3.3 4.0 mA 6.0 mA IOL 8.0 mA 10.0 m MOTOROLA 10-6 ELECTRICAL SPECIFICATIONS MC68HC705J2 6.0 m 5.0 m T = 25 C RUN MODE (OPERATING SUPPLY CURRENT (I DD ) 1.5 m T = 25C WAIT MOD 1.0 m = V DD V V SUPPLY CURRENT (I DD ) 4.0 m V 5. 5 V DD 3.0 m D VD = 4. 5 V VD = D = 4. 5. 5 5 2.0 m D .0 V VD =3 VDD =3 .6 V 0.5 m V .6 V =3 3.0 V DD D = VD 1.0 m 0 0 500 kH 1 MHz 1.5 MH INTERNAL CLOCK FREQUE (XTAL 2) / 2 MHz 0 0 500 kH 1 MHz 1.5 MH INTERNAL CLOCK FREQUE (XTAL 2) / 2 MHz Figure 10-4. Typical Supply Current vs Clock Frequency 7.0 m T = -40 to +85 VDD = 5 V 1 6.0 m ) 5.0 m SUPPLY CURRENT (I DD 5.0 m T = -40 to +85 VDD = 3.3 V 1 4.0 m SUPPLY CURRENT (I DD RU N 4.0 m 3.0 m ) 3.0 m 2.0 m IT WA 2.0 m N RU 1.0 m 1.0 m WA IT 0 0 500 kH 1 MHz 1.5 MH INTERNAL CLOCK FREQUE (XTAL 2) / 2 MHz 0 0 500 kH 1 MHz 1.5 MH INTERNAL CLOCK FREQUE (XTAL 2) / 2 MHz NOTE: Maximum STOP I DD= 100 A when V DD 5 V. = NOTE: Maximum STOP I DD= 50 A when V DD 3 V. = Figure 10-5. Maximum Supply Current vs Clock Frequency MC68HC705J2 ELECTRICAL SPECIFICATIONS MOTOROLA 10-7 10.6 Control Timing (VDD = 5.0 Vdc) Table 10-5. Control Timing (V D D = 5.0 Vdc) (VDD = 5.0 Vdc 10%, VSS = 0 Vdc; TA = TL to TH) Characteristic Oscillator Frequency Crystal Option External Clock Option Internal Operating Frequency Crystal (fosc / 2) External Clock (fosc / 2) Cycle Time RESET Pulse Width Timer Resolution (NOTE 1) Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width Programming Time per Byte NOTES: 1. The 2-bit timer prescaler is the limiting factor in determining timer resolution. 2. The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tcyc. Symbol fosc Min -- dc -- dc 480 1.5 4.0 125 (NOTE 2) 90 4 Max 4.2 4.2 2.1 2.1 -- -- -- -- -- -- -- Unit MHz fop tcyc tRL tRESL tILIH tILIL tOH, tOL tEPGM MHz ns t cyc t cyc ns tcyc ns ms IRQ (PIN tILIH tILIL Edge-Sensitive Trigger -- The minimum t ILIH either 125 ns (V DD V) or 250 ns (V DD V). The period t is =5 =3 ILIL should not be less than the number of t cyc cycles it takes to execute the interrupt service routine plus 19 t cycles. cyc IRQ1 IRQ n IRQ (MCU tILIH NORMALLY USED WITH WIRED-OR CONNECTIO Edge and Level-Sensitive Trigger -- If IRQ remains low after interrupt is serviced, the next interrupt is recognized. Figure 10-6. External Interrupt Timing MOTOROLA 10-8 ELECTRICAL SPECIFICATIONS MC68HC705J2 10.7 Control Timing (VDD = 3.3 Vdc) Table 10-6. Control Timing (V D D = 3.3 Vdc) (VDD = 3.3 Vdc 10%, VSS = 0 Vdc; TA = TL to TH) Characteristic Oscillator Frequency Crystal Option External Clock Option Internal Operating Frequency Crystal (fosc / 2) External Clock (fosc / 2) Cycle Time RESET Pulse Width Timer Resolution (NOTE 1) Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width NOTES: 1. The 2-bit timer prescaler is the limiting factor in determining timer resolution. 2. The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tcyc. Symbol fosc Min -- dc -- dc 1000 1.5 4.0 250 (NOTE 2) 400 Max 2.0 2.0 1.0 1.0 -- -- -- -- -- -- Unit MHz fop tcyc tRL tRESL tILIH tILIL tOH, tOL MHz ns t cyc t cyc ns tcyc ns MC68HC705J2 ELECTRICAL SPECIFICATIONS MOTOROLA 10-9 OSC1 1 RESET t RL IRQ 2 t ILIH tILCH 4064CYC IRQ 3 INTERNA CLOCK INTERNA ADDRESS BUS NOTES: 1. Represents internal gating of OSC1 pin. 2. IRQ pin edge-sensitive mask option. 3. IRQ pin level and edge-sensitive mask option. 4. Reset vector address of MC68HC705J2 native mode shown as timing example. FFE4 FFE4 FFE4 FFF 4 RESET OR INTERRU VECTOR FETCH Figure 10-7. STOP Recovery Timing MOTOROLA 10-10 ELECTRICAL SPECIFICATIONS MC68HC705J2 tVDDR VDD POR THRESHOLD (TYPICALLY OSC1 PIN 4064 cyc INTERNA 1 CLOCK INTERNA ADDRESS BUS1 INTERNA DATA BUS1 2 0FFE 2 0FFE 2 0FFE 2 0FFE 2 0FFE 2 0FFE 0FFF3 NEW PCH NEW PCL NOTES: 1. Internal clock, internal address bus, and internal data bus are not available externally. 2. Address of high byte of reset vector is $0FFE in MC68HC705J2 native mode and $07FE in MC68HC05J1 emulation mode. 3. Address of low byte of reset vector is $0FFF in MC68HC705J2 native mode and $07FF in MC68HC05J1 emulation mode. Figure 10-8. Power-On Reset Timing INTERNA 1 CLOCK INTERNA ADDRESS BUS1 INTERNA DATA BUS1 tRL RESET2 NOTES: 1. Internal clock, internal address bus, and internal data bus signals are not available externally. 2. Next rising edge of internal clock after rising edge of RESET initiates reset sequence. 3. Address of high byte of reset vector is $0FFE in MC68HC705J2 native mode and $07FE in MC68HC05J1 emulation mode. 4. Address of low byte of reset vector is $0FFF in MC68HC705J2 native mode and $07FF in MC68HC05J1 emulation mode. 3 0FFE 3 0FFE 3 0FFE 3 0FFE 0FFF4 NEW PC NEW PC NEW PCH NEW PCL DUMMY OP CODE Figure 10-9. External Reset Timing MC68HC705J2 ELECTRICAL SPECIFICATIONS MOTOROLA 10-11 |
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